The invention relates generally to integrated circuits, and more particularly to a memory circuit having a sense-amplifier block that receives a large number of digit lines per given block width and a method for laying out the block.
Today""s memory designers continually strive to increase the data-storage density of memory arrays. FIG. 1 is a schematic diagram of a conventional memory circuit 8, which includes multiple memory-array sections 10 and 12 and sense-amplifier blocks 13. For clarity, only two array sections 10 and 12 are shown in FIG. 1. The array sections 10 and 12 each include memory cells 14, which each include an access transistor 16 and a storage capacitor 18. Each of the cells 14 is coupled to a respective word line 20, which is driven by a respective row decoder 22. Each cell 14 is also coupled to a respective digit line 24. The digit lines 24 are arranged in laterally spaced complementary (D and {overscore (D)}) pairs 15, each pair being alternately coupled to a respective one of the sense-amplifier blocks 13 on a different side of the respective array section 10 or 12. For example, one set of aligned digit-line pairs 15a and 15b in the array sections 10 and 12 are coupled to the same one of the sense-amplifier blocks 13a, which is disposed between the array sections 10 and 12. Therefore, an adjacent digit-line pair 15c in the array section 10 is coupled to a respective one of the sense-amplifier blocks 13b, and an adjacent digit-line pair 15d in the array section 12 is coupled to a respective one of the sense-amplifier blocks 13c. (The sense-amplifier blocks 13b and 13c may also be coupled to additional respective array sections not shown in FIG. 1.) Although shown as receiving one digit-line pair 15 from each side, each of the blocks 13 may receive multiple digit-line pairs 15 from each side. The blocks 13 each include isolation circuits 27, which couple the selected array section 10 or 12 to sense amplifiers 11 during a read or write cycle.
Furthermore, each digit line 24 is coupled to the memory cells 14 in every other row of the respective array section 10 or 12. That is, one digit line 24 of respective digit-line pairs 15 is coupled to the memory cells 14 in a respective even row, and the other digit line 24 of the same digit-line pair 15 is coupled to the memory cells 14 in a respective odd row. This type of layout is known as a folded digit-line architecture, and is typically used to reduce the amount of noise on the digit lines 24. Because the circuit 8 is laid out according to a folded digit-line architecture, the memory cells 14 each occupy approximately 8 square feature sizes. (A feature size is the minimum dimension, such as a line or transistor gate width, realizable with the semiconductor process used to manufacture the circuit 8.)
Still referring to FIG. 1, in operation during a read or write cycle, one or more memory cells 14 within a selected one of the array sections 10 and 12 are addressed, and the isolation circuits 27 couple the digit lines 24 that are connected to the addressed memory cells 14 to the respective sense amplifiers 11 and isolate the digit lines 24 that are connected to the unaddressed memory cells 14 from the sense amplifiers 11. During a write cycle, data is coupled from a data bus to write drivers (both not shown in FIG. 1), which drive the data through an input/output circuit 34 onto the respective digit lines 24 and into the addressed memory cells 14. During a read cycle, the respective sense-amplifier blocks 13 couple data from the addressed memory cells 14 to the data bus through the input/output circuit 34.
FIG. 2 is a schematic block diagram of the sense-amplifier blocks 13, the array sections 10 and 12 and another array section 30, and the respective interfaces 31 therebetween. In this embodiment, each sense-amplifier block 13 receives four digit-line pairs 15 from each array section 10, 12, and includes pairs of complementary digit lines 32 that respectively correspond to the received pairs 15 of complementary digit lines 24. The isolation circuits 27 are coupled to the digit lines 24 of a respective array sections 10, 12, and 30 and to the digit lines 32. As discussed above in conjunction with FIG. 1, the respective isolation circuits 27 couple the digit lines 24 that are connected to the memory cells 14 to the digit lines 32 during a read or write cycle. Additionally, each block 13 includes a conventional input/output circuit 36, which couples the digit lines 32 to complementary I/O lines 38 during a read or a write cycle, and isolates the digit lines 32 from the I/O lines 38 otherwise. Each of the sense amplifiers 11 may also include conventional circuitry for equilibrating the digit lines 32 and the digit lines 24 before a read cycle. Each block 13 also includes a conventional PMOS sense-amplifier section 33, which includes pairs of PMOS transistors (not shown in FIG. 2) that are respectively coupled to the pairs of digit lines 32. Each block 13 further includes a conventional NMOS sense-amplifier section 34, which includes corresponding pairs of NMOS transistors (not shown in FIG. 2) that are also respectively coupled to the pairs of digit lines 32. The corresponding pairs of PMOS and NMOS transistors together form the respective sense amplifiers 11 (FIG. 1), one for each pair 15 of the digit lines 32.
Still referring to FIG. 2, the digit lines 24 emerge from the respective array sections 10, 12, and 30 in the same semiconductor layer and with a certain lateral spacing called the pitch. For example, the pitch between the digit lines 24 in the same pair 15 is a distance d1, and the pitch between adjacent digit lines 24 in different pairs 15 is a distance d2. In the illustrated embodiment, d2 is approximately 3 dl, although this ratio may be different for other array sections. The sense-amplifier blocks 13 are often constructed to receive the digit lines 24 in the same semiconductor layer and at the same pitch at which they emerge from the respective array section. Therefore, the blocks 13 are typically constructed so that along any one side of a respective array section, the sum of the respective widths w of all the blocks 13 adjacent to this array side are no more than the width W of the array. Thus, the array sections 10, 12, and 30 and the blocks 13 occupy the same total width so as to use the layout area of the circuit 8 in an efficient manner. This geometry inherently limits the number of digit lines 24, 32 that can extend through the array sections 10, 12, 30 and the blocks 13.
Referring to FIG. 3, one way to increase the data-storage density of a memory circuit is to layout the array sections according to a bi-level digit-line architecture. Generally, the density of an array section is limited by the lateral spacing of digit lines. In the bi-level architecture, the array sections include additional layers of digit lines stacked on top of each other. In such an architecture, bi-level digit lines 42 in the same complementary pair 43 are located in different semiconductor layers so that one digit line 42 of the pair 43 is disposed atop the other digit line 42 of the same pair 43. As the digit lines 42 emerge from the array section, however, the digit lines 42 of each pair 43 may be routed such that they are in the same semiconductor layer. This architecture allows the memory cells 14 (FIG. 1) to each have an area of approximately 6 square feature sizes instead of the approximately 8 square feature sizes required by each memory cell 14 in the folded-digit-line circuit 8 of FIG. 1. But, because the bi-level architecture allows an additional layer of digit lines 42 within a given area, the bi-level architecture also increases the density of the digit lines 42 in each array section. This bi-level digit-line architecture is discussed more in detail in xe2x80x9cA Novel Architecture for Advanced High Density Dynamic Random Access Memories, A Thesis Presented in Partial Fulfillment of the Requirements for the Degree of Master of Science with a Major in Electrical Engineering in the College of Graduate Studies University of Idahoxe2x80x9d by Brent Keeth (May 1996), which is incorporated by reference.
FIG. 4 is a proposed schematic block diagram of a memory circuit 41 that includes array sections 44 laid out according to a bi-level digit-line architecture and coupled to the sense-amplifier blocks 13. (Bi-level digit line architecture is an architecture that has been designed only recently, and a memory circuit using the bi-level architecture that includes sense-amplifier blocks has not yet been developed.) Referring to FIGS. 3 and 4, as they emerge from the side of the respective array 44, the digit lines 42 are routed with a tighter pitch than the laterally spaced digit lines 24 of FIG. 1. Additionally, the digit lines 42 are disposed in the same semiconductor layer as they emerge from the respective array section 44. So that the bi-level array section 44 can be constructed to have a width that is the same or smaller than the width W of the array sections 10, 12, and 30 of FIG. 2, the pitch d3 between digit lines 42 of the same digit-line pair 43 is approximately the same as the pitch d4 between adjacent digit lines 42 of different pairs 43. Typically, the pitches d3 and d4 are equal to the pitch d1 of FIG. 1. Therefore, the array sections 44 each have a width that is approximately equal to the width W even though the array sections 44 each include twice the number of digit lines as each of the array sections 10, 12, and 30 of FIG. 2.
Still referring to FIG. 4, a problem with this layout is that it is difficult to use the sense-amplifier blocks 13 with the array sections 44. For example, because the array sections 44 each have twice the number of digit lines 42, the memory circuit 41 has twice as many sense-amplifier blocks 13. Therefore, the combined widths w of the sense-amplifier blocks 13 are equal to at least 2 W, which is at least twice as wide as the widths of the array sections 44. Therefore, the array sections 44 in a same column of array sections would be separated by respective areas having widths of at least W. Furthermore, because it would be difficult to form circuitry in these separation areas, these areas would significantly increase the overall area of the memory circuit 41, perhaps even by an amount greater than the area savings realized by the array sections 44 having the bi-level architecture. Additionally, as discussed above in conjunction with FIG. 2, the blocks 13 are constructed to receive digit lines at a pitch of d1 between digit lines of the same pair and at a pitch of d2 between adjacent digit lines of different pairs. Therefore, the digit lines 42 must be routed according to these pitches after they emerge from the array sections 44.
Although the above discussion focuses primarily on a bi-level architecture, similar problems would also be experienced with array sections 44 having more layers of digit lines 24 than two, such as a tri-level architecture. In fact, as each layer of digit lines 24 is added, the problem is worsened as the additional digit lines 24 require additional sense-amplifier blocks 13. Each additional sense-amplifier block 13 increases the width of the separation areas between the array sections 44, significantly increasing the overall area of the memory circuit 41. Similarly, this problem can exist for all types of layout configurations for array sections 44, such as open digit line and folded digit line architecture.
In one aspect of the present invention, a memory circuit includes first and second amplifier stages that are respectively located within first and second regions of a semiconductor structure, and a memory array that is also located in the semiconductor structure. The memory circuit also includes a first set of digit lines that is coupled to the memory array, extends from the memory array into the first region, and is coupled to the first amplifier stage. The memory circuit further includes a second set of digit lines that is coupled to the memory array, extends from the memory array through the first region and into the second region, is coupled to the second amplifier stage, and is electrically isolated from the first amplifier stage.
Such a memory circuit can incorporate bi-level array sections without large separation areas therebetween.